Tuesday, 14 February 2023
Sunday, 12 February 2023
Temps Utile - basic (micro temps)
When you power the module up you will enter the global input configuration.
Using a micro temps here
To reach the Main (channel) page
1. long press the right encoder.
2. scroll to the saved setting you want to recall using the right encoder.
(in this case 6 clocks)
3. press the right encoder.
To set the BPM
1. press the left (up button once)
2. turn the right encoder to adjust the BPM
Saturday, 11 February 2023
MITL 2023 - part 2
Some pics from the last modular in the Lounge.
Held in a secret location in Sydney Australia.
..
Tuesday, 7 February 2023
Monday, 6 February 2023
Voltage memory - Meng Qi
some build pics & notes
Links
+ Manual
+ BOM
Uses ths microconroller
It uses these 3 pairs of DACs
MicroChip 2 MCP4725A0T-E/CH DAC SOT32-6
MicroChip 2 MCP4725A1T-E/CH DAC SOT32-6
MicroChip 2 MCP4725A2T-E/CH DAC SOT32-6
Some SMD components
BAT85 Schottky Diode 30V 200mA
BAT54ht1-g
using these instead
https://www.onsemi.com/pdf/datasheet/bat54ht1-d.pdf
This could be the problem ????
Remove RX LED
Solder to the Seeeduino ... pad 17
I uploaded the firmware successfully
but the module fails to boot.
???
trouble shoot when I have more time in the future.
Sunday, 5 February 2023
Make noise Rene V1 - Logic
The logic functions of the Rene are accessed with these 9 pads:
To enter the logic settings you'll need to access the X-fun or Y-fun pages
The 3 rows of the logic processing can be divided into
1. CLK by MOD,
2. Gate by MOD
3. Gate by Opposing CLK.
WE need to send pulses & Clocks into the Clk & the MOD inputs
(for the respective X & Y gate outputs).
The logic setting will influence the final gate outputs.
1. CLK by MOD
With the Clock Logic Ops (locations 9, 10, 11) the MOD input is AND, OR, XOR against
the CLocK and the result drives the counter for the associated Axis.
For CLK by MOD logic operations the results apply to both the movement of the
sequence and the associated gate outputs.
AND OR XOR
2. Gate by MOD
With the Gate Logic Ops (locations 5, 6, 7) the MOD is AND, OR, XOR against the CLocK
and the result drives the gate programming logic (X Gate or Y Gate pages).
For Gate by MOD logic operations the results apply only to the associated
gate outputs.
AND OR XOR
3. Gate by Opposing CLK.
Here, the inputs are the X and Y clock inputs
So it's impt that the clocks are running at different speeds
--------------
Note:
One parameter that has a great deal of bearing on the outcome of these logic processes is
Gate Width of the incoming CLocK and MOD signals.
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