The logic functions of the Rene are accessed with these 9 pads:
To enter the logic settings you'll need to access the X-fun or Y-fun pages
The 3 rows of the logic processing can be divided into
1. CLK by MOD,
2. Gate by MOD
3. Gate by Opposing CLK.
WE need to send pulses & Clocks into the Clk & the MOD inputs
(for the respective X & Y gate outputs).
The logic setting will influence the final gate outputs.
1. CLK by MOD
With the Clock Logic Ops (locations 9, 10, 11) the MOD input is AND, OR, XOR against
the CLocK and the result drives the counter for the associated Axis.
For CLK by MOD logic operations the results apply to both the movement of the
sequence and the associated gate outputs.
AND OR XOR
2. Gate by MOD
With the Gate Logic Ops (locations 5, 6, 7) the MOD is AND, OR, XOR against the CLocK
and the result drives the gate programming logic (X Gate or Y Gate pages).
For Gate by MOD logic operations the results apply only to the associated
gate outputs.
AND OR XOR
3. Gate by Opposing CLK.
Here, the inputs are the X and Y clock inputs
So it's impt that the clocks are running at different speeds
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Note:
One parameter that has a great deal of bearing on the outcome of these logic processes is
Gate Width of the incoming CLocK and MOD signals.
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